The present invention relates to semiconductor switching devices.
A switching device includes a four terminal device, which couples its output node to any one of two available voltage sources based on an input level. A three terminal switch in electrical applications is a light bulb switch: output connects to power when the input is on, and open circuit when the input is off. Common 4 terminal switches in the semiconductor industry include single input inverters and 2:1 MUXs. The inverter and MUX output switches between two voltage levels based on the input voltage level. In the inverter, the output voltage has an opposite polarity to the input voltage. Inverters can be classified into three types: full CMOS inverter, resistor load inverter, and thin film PMOS load inverter. A Depletion load inverter is not commonly used in sub micron geometries. It is not discussed in detail in this disclosure. The common inverter is used for boosting signal levels, and constructing latches. A latch consists of two inverters connected back to back and allows storing digital data when the latch is powered. These latches are used to build static random access memory (SRAM) devices. Very high density SRAM memory is used in Integrated Circuits to store and access large amounts of digital data very quickly.
A switching device fabrication in single crystal Silicon (Si) has two different methods. The most popular CMOS inverter in FIG. 1 has two MOSFET transistors. Fabrication comprises a simple Logic Process flow with no special processing needed. Both transistors are located in a substrate single crystal Silicon, and have high mobilities for electron and hole conduction. This inverter area is large, standby current is negligible and the output current drive is very good. This inverter configuration is used for high cost, least power, fastest access SRAM memory, and for data buffering and high current output drivers.
In FIG. 1, the inverter contains two voltage sources 103 and 104. These are typically VD (power) and VS (ground) respectively, but do not need to be so. The switch has an input voltage 101, and an output voltage 102. A PMOS 110 is connected between voltage source 103 and output node 102, and an NMOS 120 is connected between output node 102 and voltage source 104. Both transistor gates are tied together for a common input 101. When the input is at logic 1 (VD), the NMOS device is on and the PMOS device is off, connecting voltage source 104 to output 102. When the input is at logic 0 (VS), the NMOS is off and PMOS is on connecting source 103 to output 102. As both NMOS and PMOS have high mobility, the current drives via the transistors are very high. The output is driven very strongly to one of the two voltage supply levels. Any deviations from these values are corrected very quickly via the conducting transistors. If VD and VS were two other voltage levels V1 and V2, the device in FIG. 1 is a 2:1 CMOS MUX with input 101 and output 102.
The CMOS inverter consumes a relatively large amount of Silicon area. FIGS. 2A and 2B show a conventional CMOS inverter fabricated using a conventional twin well process. Both PMOS and NMOS devises comprises a conducting path and a gate. In FIG. 2A, NMOS conducting path is 220, while PMOS conducting path is 210. Both NMOS and PMOS share a common gate 201. NMOS conducting path 220 is inside a P-well 230, while PMOS conducting path 210 is inside an N-well 240. PMOS source and drain diffusions 211 and 212 are P+ diffusion regions, while NMOS source and drain diffusions 214 and 213 are N+ diffusion regions. Conducting path include these source and drain diffusions. Due to potential latch-up conditions, a separation distance Y is maintained between the two conducting paths 210 and 220. Hence the two devices are constructed on two separate active geometries on the substrate 250. Both Nwell 240 and Pwell 230 are constructed on a substrate 250 of the device, which could be P-type or N-type. Latch-up arises from the P+/N-well/P−Well regions 212/240/230 and N+/P−Well/N-well regions 213/230/240 bipolar parasitic transistors near the well boundary as shown in FIG. 2B. In FIG. 2B, PMOS source 211 and body 240 are tied to VD 203, and NMOS source 213 and body 230 are tied to VS 204. In other applications, the body may be separately biased. The Pwell 230 has to be biased to the lowest potential, while the Nwell 240 has to be biased to the highest potential.
In addition to the CMOS approach, the inverter can be fabricated as a Resistor-load inverter and a TFT PMOS-load inverter. They both have the pull-up device vertically integrated and require special poly-crystalline (poly) silicon for the load device construction. The pull-up devices in FIGS. 3A and 3B are poly Silicon resistor 310, and TFT PMOS 3010 respectively and are not built on single crystal silicon. The pull-down NMOS device conducting paths 320 and 3020 remain in single crystal silicon. The vertically integrated pull-up device allows elimination of N-wells in the substrate, and a smaller inverter construction area. Latches constructed with these inverters consume standby power as one inverter is always conducting, and the power consumption is determined by the resistor value. For 1 Meg density of latches and 1 mA standby current, a resistor value of 1 GOhms is needed. High value intrinsic poly-silicon resistors are hard to build, and TFT PMOS devices offer better manufacturability. TFT PMOS can be also used as active weak PMOS pull-up devices similar to regular PMOS in FIG. 1 to eliminate stand-by current. As the pull-up device 310 or 3010 drive current is very weak, these inverters cannot drive a strong logic one. These configurations of inverters are only used to build latches to construct low cost, high density, higher power, and medium access SRAM memory. Such memories need complex dual ended sense amplifiers to read the latch data.
Inverters in FIGS. 1 and 3 can be constructed with Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) devices, which is a sub-class of more generic Insulated-Gate Field-Effect Transistor (IGFET). The inverter in FIG. 1 cannot be constructed with Junction Field Effect Transistors (JFET) due to the voltage restrictions on the gate as discussed below.
The MOSFET operates by conducting current between its drain and source through a conducting surface channel created by the presence of a gate voltage. FIG. 4 shows a cross section of an N-MOSFET (NMOS) conducting channel 410 with a depletion region shown shaded. In FIG. 4, an NMOS transistor body 400 is P− doped, isolating an N+ doped source region 414 and an N+ doped drain region 413. Source and drain diffusions are connected to terminals 404 and 403 respectively. The result is the formation of two N+/P− back-to-back reverse-biased diodes. For this discussion, the source 404 is assumed at zero (VS). When the voltage 402 at gate 412 is zero, the N+/P− back-to-back reverse-biased diodes do not conduct and the transistor is off. There is no surface channel 410, and the body surface under insulator 405 next to gate 412 is in accumulation of majority hole carriers. The conduction path between source and drain is now substantially non-conductive. In the embodiment of FIG. 4, the gate 412 includes a salicided region 422. A spacer 420 is formed adjacent to gate 412. Source and drain salicidation is not shown in FIG. 4. When the gate voltage 402 is greater than a threshold voltage (VT) of the transistor, an inversion occurs near the surface, shown by channel 410, completing an electron carrier path between the source 414 and drain 413 regions causing current flow. The conducting path now include source 414, channel 410 and drain 413 and is substantially conductive. In addition to the inversion layer, charge depletion occurs adjacent to the body region 400 due to the gate, source and drain voltages. The component of this depleted charge from the gate voltage determines the magnitude of the VT. Trapped oxide charge and Silicon defects affect the VT transistor parameter. The more positive the voltage is at the gate, the stronger is the conduction. At all levels, the substrate 400 potential is kept at the lowest voltage level. In most applications, the substrate and source are held at VS. Substrate can be pumped to negative voltages for special applications.
A PMOS device is analogous to an NMOS device, with the device operational polarity and doping types reversed. PMOS source is typically tied to VD. A PMOS is on when the gate is at VS, and off when the gate is at VD. Conducting path includes a P+ doped source and drain, and a surface inversion layer in the Nwell body region. The Nwell is biased to the highest potential, and in most applications the source and Nwell are held at VD.
As discussed in U.S. Pat. No. 5,537,078, conventional JFET transistors are of two main types: P-channel (PJFET) and N−channel (NJFET). In NJFET, FIG. 5, a semiconductor channel 506 which has been doped N− is positioned between two N+ diffusions 513 and 514. Conducting path includes diffusion 513, resistive channel 506 and diffusion 514. Terminals 503 and 504 are coupled to diffusions 513 and 514. The terminal supplying the majority carrier to the channel (which is the lowest potential) is designated the source (S) while the other terminal is designated the drain (D). Across the N− channel 506 there are two diffused gates which are referred to as the top gate 512 and the bottom gate 522. Those are connected to terminals 502 and 532 respectively. Each gate is doped with P+ type dopant to create two back to back P+/N− diodes. When drain and source voltages are different, the drain to source current passes entirely through the conducting N− channel 506. This current increases with higher voltage drop between the terminals, reaching a saturation value at high biases. The gates are biased to keep the gate to channel P+/N− junctions reversed biased. The reversed biased voltage creates depletion regions 510 and 520 that penetrate into the channel reducing the channel height available for current flow. The depletion regions merge at drain end 530 to cause current saturation at high drain bias. The gate voltages also control the flow of current between the source and drain by modulating the channel height. When the gate reverse bias is sufficiently large, the entire channel is pinched-off causing no current flow between drain and source. Conducting path is then substantially non-conductive. In both on and off states of a JFET, there is no current flow through the gate terminal due to reverse bias junction voltages, except for junction leakage current. For the device in FIG. 5 a negative gate voltage (lower than VS) creates the channel off condition. Such a negative gate voltage increases the operating voltage of this process, a draw back for JFET scheme.
A PJFET device is analogous to an NJFET device, with the device operational polarity and doping types reversed. PJFET source is held at VD. A PJFET is on when the gate is at VD, and off when the gate is more positive than VD increasing the voltage level of the process. Conducting path includes P+ doped source and drain regions, and a P− doped channel sandwiched between two N+ doped gate regions. For terminals at voltages VS and VD, operating range of NJFET gate is less than VS to VS, while the operating range for PJFET gate is VD to more than VD. This non-overlapping gate voltage prevents having a common gate input.
Compared to the non-conducting body 400 of MOSFET on FIG. 4, the JFET has a conducting channel 406 between source and drain. Due to non-overlapping gate voltages and the high voltage range thus needed, a complementary JFET process is impractical to realize. Hence there is no low cost process that provides CJFET devices analogous to CMOS devices. Compared to the MOSFET in FIG. 4, a JFET conducting channel is formed inside the body of the switching device. This channel current is not affected by trapped oxide charges near the gate, a draw back with MOSFETs. Compared to MOSFETs, JFETs also have poorer switching characteristics due to higher depleted charge stored in the channel and the transient times required to accumulate and disperse this depletion charge. Reverse biased junctions hurt JFET device ease of use and popularity in modern day ICs.
For the discussion that follows, the terminology Gated-FET device is used. A gated-FET device is defined as a mixed device between a conventional MOSFET device and a conventional JFET device. The Gated-FET device conducting channel is like that of JFET devices: entirely comprising of a thin film resistive channel between the source and drain regions. There is no inversion layer like in a MOSFET to conduct current. The Gated-FET device gate is like that of a MOSFET device: the gate constructed above a dielectric material and capable of modulating the thin film channel conduction. There is no gate junction like in a JFET to reverse bias the channel. The Gated-FET device is disclosed in detail in the application “Insulated-Gate Field-Effect Thin Film Transistors”.